The present invention relates to semiconductor wafers used in the manufacture of semiconductor devices, and apparatus for the processing of such semiconductor wafers.
Normally, oxidation and diffusion processing, CVD processing and other types of processing are used in the manufacture of semiconductor devices.
In particular, there has been recent increase in the degree of fineness of the design for semiconductor devices, where device element dimensions have changed from 0.4 .mu.m to 0.2 .mu.m. In addition, the semiconductor wafers themselves have been becoming larger, and have changed from 8 inches to 12 inches in diameter. One important problem is the development of technologies for fast heat treatment which can be used with technologies for the growth of extremely thin films over such a larger area on the semiconductor wafer.
More specifically, in semiconductor wafer process processing, one necessary condition is that the thermal budget (or the heat history) be made as small as possible. For example, in the growth of an extremely thin film of a capacitor insulation film or a gate oxidation film by doping processing for 50-100 .ANG., it is essential that the heat treatment be performed quickly, that is, in as short a time as possible.
Not only this, PN junctions for example, have been becoming as thin as 0.1 .mu.m or less, and enabling them to have lower resistances, and the growth of junctions to surfaces of arbitrary shapes requires that the generation of crystal faults be prevented along with the deterioration of the film when the junction is made. However, the active region of PN junctions is narrow and so it is again necessary that the heat treatment be performed as quickly as possible.
In addition, in the growth of a LOCOS oxidation film for example, the synergetic effect of compression stresses in adjacent LOCOS oxidation films is magnified due to the heat cycle and it is easy for changes in the surface potential, leak currents, and reduction of the resist voltage reliability to occur. With respect to these problems, it is necessary to prevent them by reducing the heat cycle by having fast heat treatment of semiconductor wafers.
Also, when there is the use of, for example, materials having a highly dielectric compounds in the growth of a capacitor insulation films, it is necessary to have a system which enables compound process processing by enabling doping and metal film growth to enable the growth of metal oxides (such as Ta.sub.2 O.sub.5 and the like) and polyamides (passivation films).
Thus, the current status of the technology is that semiconductor wafers are becoming larger from 8 inches to 12 inches, and that it is necessary to have fast and uniform heating while reducing the temperature differential between the central and the peripheral portions of the semiconductor wafer, reducing the occurrence of slip, distortion and warping which easily occur in semiconductor wafers, and to prevent them from becoming a hindrance in the manufacture of semiconductor devices.
However, in the heat treatment of a semiconductor wafer having a diameter of more than 10 inches for example, it is easy for processing gas to remain on the processing surface of the semiconductor wafer and to create problems of thermal distortion and faulty film growth to the wafer.
With respect to this, the inventors have researched the solution of these problems by improving the heat treatment apparatus for the semiconductor wafers, but also by improving the semiconductor wafer itself. Then, it was discovered that through an extremely simple configuration wherein a through hole was provided in the center portion of the semiconductor wafer which enables the prevention of residual processing gas on the processing surface of the semiconductor wafer and thus the present invention was completed.
In the field of processing of semiconductor wafers, it is necessary to increase the throughput so as to correspond to recent increases in demand and because of this, it is necessary to convey semiconductor wafers in a status of high speed and high accuracy.
In addition, the recent increase in the diameter of semiconductor wafers requires that semiconductor wafers having such large areas be conveyed suitable and at high speed.
However, semiconductor wafers have conventionally been simply loaded to a conveying apparatus and conveyed and so position discrepancies occur between semiconductor wafers when they are moved at high speed by a conveyor apparatus and there was the problem of the position accuracy deteriorating. In addition, there was also the problem of the semiconductor wafers chipping when their positions were displaced and so a conventional conveyor means involved the difficulty of conveying the semiconductor wafers at high speed, and there was no choice but to convey the semiconductor wafers at low speed.
The following is a more specific description of this, with reference to the loading fork 91 shown in FIG. 21 and which is used as the conventional means of loading the semiconductor wafers. This loading fork 91 is provided with a step 92 to load the semiconductor wafer 1 and to hold a peripheral portion of its rear side. To the peripheral portion of the step 92 is provided a protrusion 93 for positioning the semiconductor wafer 1. Then, as shown in FIG. 22, the loading fork 91 is configured so that it is mounted to the conveyor platform 95, rotationally moves in the X, Z and .theta. directions, takes a semiconductor wafer 1 from the wafer cassette 1a and moves it to the wafer boat 100. However, there is a slight clearance between the two so that the semiconductor wafer 1 can be easily loaded to the step 92 and so when there is conveying at high speed, it becomes difficult to completely prevent position discrepancies along the surface of the semiconductor wafer.